RISC-V CPU in HLS

This project was an attempt to explore the usefulness of high level synthesis tools for control heavy algorithms, such as general purpose processors. Our hypothesis that we wanted to specifically explore was that HLS tools would be more successful pipelining an out of order processor design than an simple top level sequential model. This hardly was the case, as we discovered the lack of clocking mechanisms in Vivado HLS was not sufficient to describe the concurrent out of order model of our intended CPU. Nonetheless, this project was a great experience in pushing the boundaries of what is believed to be possible and learning more about HLS and architecture generally.

The powerpoint gives a good overview of the project. The paper can be found below that with more info.