PUC: An Out of Order CPU

As a final project for a computer architecture course, me and my team were able to tackle the problem of implementing the RISCV ISA as an out of order CPU. We utilized the Tomasulo algorithm that renames registers into a reorder buffer at instruction dispatch, dynamically creates a dependency graph through these renamings, and executes instructions (sometimes out of order....) in various functional units. It was an exciting and fun task to design, implement, and validate our design using SystemVerilog. Synthesis, timing, and power analysis tasks were done using Quartus tools.

Check out the slides for a quick overview of the results of our work. Dig into the process a bit more in the "formal" report.